| Esencia IP cores are among the best performance, low gate count available in the market. Each of these IP cores can be configured for several performance/area trade-offs to meet the customer requirements | |
| DSP Communications domain | |
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FFT 1024/512: Low latency, dynamically configurable as 1024 or 512 points FFT and IFFT. Ideal for WiMax and MIMO applications. Detailed datasheet can be downloaded from  here. |
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FFT 64/128: Low latency, 64 point FFT and IFFT. Parameterized bit widths and fixed point option. Supports flushing and re-starting the FFT operation instantly. Detailed datasheet can be downloaded from here. |
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Viterbi Decoder: Viterbi Algorithm for 802.11 a/b/g standard. Low gate count implementation. Option to optimize on flush latency with additional hardware. Detailed datasheet can be downloaded from here. |
| Security domain(Encryption and Authentication) | |
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AES: High speed Advanced Encryption Standard. Supports AES FIPS 197 encryption and decryption. Detailed datasheet can be downloaded from here. |
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DES: Low-gate count Data Encryption Standard. Supports both encryption and decryption. Can be configured to implement Triple-DES. Detailed datasheet can be downloaded from here. |
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SHA-1 hash: High speed data authentication. This IP core supports the Secure Hash Algorithm described in RFC 3174. Detailed datasheet can be downloaded from here. |
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MD5: High Speed data authentication. This IP core supports the MD5 Secure Hash Algorithm described in RFC 1321. Detailed datasheet can be downloaded fromhere. |
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ARC4: Multi-threaded stream ciphering algorithm. This IP core supports simultaneous encryption/decryption of multiple independent sessions in a time-multiplexed fashion. Detailed datasheet can be downloaded from here. |
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