Job Requirements and Qualification

You must have a MSEE or PhD with at least 7+ years of relevant experience. Demonstrate successful results in multiple DSP programs is required. Strong written and verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of algorithm design and modeling methodologies in Matlab.

Minimum Requirements

• Excellent understanding of  DSP and wireless and wired communication theory
• Excellent understanding of ASIC implementation aspects of DSP algorithms
• Experienced in verification aspects of data and control plane RTL implementation
• Proficient in Matlab coding
• Ability to work with cross-functional teams to troubleshoot regression test failures

Preferred Requirements

• Familiarity with OFDM, WiFi, LTE or similar communication standards is a plus
• Familiar with ASIC design flows for deep sub micron technologies
• UVM/OVM Verification Methodology

Responsibilities

In this role, the candidate will work with system engineers to architect, specify and design signal processing algorithms in most effective ways.  The Candidate needs to understand all aspects of DSP ASIC implementations  and must be able to decide on trade-offs between clocking, area and power.

Responsibilities include:

Perform DSP algorithm feasibility studies and performance evaluations and summarize findings in technical reports and presentations. Participate in fix-point algorithm refinement with system engineering teams. Generate data plane block diagrams and specifications. Generate gate count estimates and maintain them. Coach RTL engineers coding DSP blocks.

This Job is located in San Jose, California Metropolitan Statistical Area. Candidate must have the legal right to work in the USA.

Please refer to Job Number ESE13-0321 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
2150 North First Street, Suite #680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0321
E-mail: hr@esenciatech.com

Job Requirements and Qualification

You must have a MSEE or PhD with at least 7+ years of relevant experience. Demonstrate successful results in multiple ASIC DSP programs is required. Strong written and verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Matlab, Synopsys and Cadence design tools and flows.

Minimum Requirements

• Excellent understanding of  DSP and wireless and wired communication theory
• Excellent understanding of ASIC implementation aspects of DSP algorithms
• Experienced in verification aspects of data and conrol plane RTL implementation
• Excellent Verilog, SystemVerilog, VHDL coding skills
• Proficient in Matlab coding
• Hands on experience with Cadence and Synopsys design and synthesis tools
• Ability to work with cross-functional teams to troubleshoot regression test failures

Preferred Requirements

• Familiarity with OFDM, WiFi, LTE or similar communication standards is a plus
• Familiar with ASIC design flows for deep sub micron technologies
• UVM/OVM Verification Methodology

Responsibilities

In this role, the candidate will work with system engineers to architect, specify and design signal processing algorithms in most effective ways.  The Candidate needs to understand all aspects of DSP ASIC implementations  and must be able to decide on trade-offs between clocking, area and power.

Responsibilities include:

Participate in fix-point algorithm refinement with system engineering teams. Generate data plane block diagrams and specifications. Generate gate count estimates and maintain them. Coach RTL engineers coding DSP blocks. Conduct RTL code reviews.

This Job is located in San Jose, California Metropolitan Statistical Area. Candidate must have the legal right to work in the USA.

Please refer to Job Number ESE13-0301 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
2150 North First Street, Suite #680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0301
E-mail: hr@esenciatech.com

Job Requirements and Qualification

You must have a BSEE or MSEE with at least 5+ years of applicable experience. Demonstrate successful results for multiple ASIC programs, is required. Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Synopsys and  Cadence design tools and flows.

Minimum Requirements

• Direct hands-on experience on top level complex SoC floorplan
• Hands on experience with Synopsys Jupitor XP and ICC tols
• Integration of Various IP’s including: MIPI, USB, I2C, GPIO, DDR etc
• Ability to work with cross-functional teams to troubleshoot floorplan  and packaging issues
• Familiarity with ASIC design flows for deep sub micron technologies
• Familiarity with deep sub-micron design rules

Preferred Requirements

• Familiarity with image processing is a strong plus

Responsibilities

In this role, the candidate will work with the designers to integrate the design into floorplan.  The Candidate needs to understand the complexity of integrating various IP’s and IO pad ring generation. A candidate will work with the ASIC design team to understand the IP area and SoC gate area to come up with an optimized die-size.
Responsibilities include:

Generate/Optimize pad ring, core by working with cross-functional teams including front-end designs, package design, and System board design teams. A candidate will design the floorplan by integrating the gate-level netlist and timing constraints.  Estimate/Optimize chip / die size.  Work with engineers to identify IO ring and IO voltage domains.  Familiarity with EM (ElectroMigration) and SSO (Simultaneously Switching Output) checks.  Support synthesis teams with feedback from the Place and Route perspective and integration.

This Job is located in Chandler / Arizona Metropolitan Statistical Area. Candidate must have the legal right to work in the USA .

Please refer to Job Number ESE13-0202 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
2150 North First Street, Suite #680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0202
E-mail: hr@esenciatech.com

For functional verification coverage, we specify coverage points for each feature indicated in the specification, so there is direct mapping–and hence, there are good metrics–for completeness criteria. However, for assertions, we have not been able to specify such measurable criteria for completeness.

This is partly because assertions aim at states and signal combinations that are not allowed to occur. Most of the specifications I have come across do not consider those in great detail, which then makes it challenging to come up with the right set of assertions quickly.

Therefore, it looks like it pays off to be more rigorous in specifying illegal combination and state transitions in the requirements specification. With this in hand, we are then able to derive the assertions the same way we do for coverage points–and use the same completeness metrics.

I am curious about what other experts practice and have to say about this matter, so please leave a note if you would like to share your thoughts.

Job Requirements and Qualification

This position provides a unique opportunity in a global research team working on moving an innovative processor core architecture into production.

Minimum Requirements:

• Candidate must possess a Masters or a Bachelor degree in Computer Science or a related field
• At least 5 years of relevant experience. (Note: we cannot consider resume with less work experience)
• Knowledge of OS internals, Intel 64 instruction set architecture and system architecture.
• Experience in compiler optimization, performance analysis, computer architecture, micro-architecture, binary translation and processor simulation
• Experience with performance analysis tools and pipetrace viewers, C/C++,  modern scripting languages, x86 assembly

Responsibilities

The successful candidate will perform performance analysis on a wide range of benchmarks and application workloads. The analysis will target compiler optimizations in a dynamic binary translator, optimization sensitivity studies, and comparative architectural analysis across families of x86 processors, both single and multi-core. It is expected that the successful candidate will also push for improving workload performance by working with binary translator and architecture teams, will help with identification and bring-up of new workloads and be available for travel.

This Job is located in Silicon Valley / San Jose, CA Metropolitan Statistical Area. Candidate must have the legal right to work in the USA .

Please refer to Job Number ESE13-0201 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
2150 N. First Street, Ste. 680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0201
E-mail: hr@esenciatech.com

Job Requirements and Qualification

You must have a BSEE or MSEE with at least 5+ years of applicable experience. Demonstrate successful results for multiple ASIC programs, is required. Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Synopsys and  Cadence design tools and flows.

Minimum Requirements:

• SOC level Synthesis / STA.
• Experienced with Verilog/VHDL digital design
• Hands on experience with constraints development
• Hands on experience with Synopsys design compiler and ICC
• SoC implementation experience such as full chip level synthesis Pre-P&R timing closure
• Hands on experience with Spyglass rule checking, netlist equivalence checking, and gate-level simulations
• Experience with various synthesis options to optimize the power of the Design.
• Work with Place and Route peers for timing closure
• Good Knowledge of Static Timing Analysis and Place and Route.
• Familiarity with various interface technologies including MIPI, USB, I2C, GPIO, DDR etc
• Familiarity with ASIC design flows for deep sub micron technologies
• Familiarity with FPGA design flow is plus

Preferred Requirements:

• Familiarity with image processing is a strong plus

Responsibilities

In this role, the candidate will work with designers and understand the complexity of the blocks and interfaces. A candidate will work with the ASIC design team and will participate in the development of netlist generation from synthesis. A candidate will also support  the design team to do simulations .

Responsibilities include: reading the RTL code. Generating chip level timing constraints. Validating the RTL inputs.  Analyzing the power for the design and optimizing for speed/area/power.  Understand and drive the pre-synthesis chip-level timing to ensure that synthesis and layout level timing and other specifications can be achieved.

Support chip level verification and physical design timing closure.

This Job is located in Silicon Valley / San Jose, CA & Metropolitan Statistical Area. Candidate must have the legal right to work in the USA .

Please refer to Job Number ESE13-0104 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
2150 North First Street, Suite #680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0104
E-mail: hr@esenciatech.com

Job Requirements and Qualification

You must have a BSEE or MSEE with at least 5+ years of applicable experience. Demonstrate successful results for multiple ASIC programs, is required. Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Synopsys and  Cadence design tools and flows.

Minimum Requirements

• Direct hands-on experience on top level complex SoC floorplan
• Hands on experience with Synopsys Jupitor XP and ICC tols
• Integration of Various IP’s including: MIPI, USB, I2C, GPIO, DDR etc
• Ability to work with cross-functional teams to troubleshoot floorplan  and packaging issues
• Familiarity with ASIC design flows for deep sub micron technologies
• Familiarity with deep sub-micron design rules

Preferred Requirements

• Familiarity with image processing is a strong plus

Responsibilities

In this role, the candidate will work with the designers to integrate the design into floorplan.  The Candidate needs to understand the complexity of integrating various IP’s and IO pad ring generation. A candidate will work with the ASIC design team to understand the IP area and SoC gate area to come up with an optimized die-size.
Responsibilities include:

Generate/Optimize pad ring, core by working with cross-functional teams including front-end designs, package design, and System board design teams. A candidate will design the floorplan by integrating the gate-level netlist and timing constraints.  Estimate/Optimize chip / die size.  Work with engineers to identify IO ring and IO voltage domains.  Familiarity with EM (ElectroMigration) and SSO (Simultaneously Switching Output) checks.  Support synthesis teams with feedback from the Place and Route perspective and integration.

This Job is located in Silicon Valley / San Jose, CA & Metropolitan Statistical Area. Candidate must have the legal right to work in the USA .

Please refer to Job Number ESE13-0101 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
2150 North First Street, Suite #680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0101
E-mail: hr@esenciatech.com

Job Requirements and Qualification

You must have a BSEE or MSEE with at least 5+ years of applicable experience. Demonstrate successful results for multiple ASIC programs, is required. Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Synopsys and  Mentor design tools and flows.

Minimum Requirements

• Working with rest of the team to document DFT specifications
• Developing and implementing DFT architecture
• Implementing DFT structure
• Working with the Design Implementation team to verify DFT implementations and implement ECOs
• Generating structural test vectors and analyzing and improving coverage
• Working with designers on STA, physical, power and logical issues
• Working with test engineers to bring up test vectors on test-house/silicon
• Managing schedules and supporting cross-functional engineering effort

Preferred Requirements

• Familiarity with image processing is a strong plus

Responsibilities

In this role, the candidate will lead the Design-for-Test Architecture to develop and deploy test concepts for a high speed ASIC.  Work closely with the silicon and RTL design engineers to develop and implement design for test for the ASIC part, using scan, bist, logic bist and redundancy techniques.

Support chip level verification and physical design timing closure.

This Job is located in Silicon Valley / San Jose, CA & Metropolitan Statistical Area. Candidate must have the legal right to work in the USA .

Please refer to Job Number ESE13-0102 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
2150 North First Street, Suite #680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0102
E-mail: hr@esenciatech.com

Job Requirements and Qualification

You must have a BSEE or MSEE with at least 5+ years experience in developing and owning full chip Timing Constraints for a complex, multi-clock, multi-voltage SoCs . Experience in running STA analysis and achieving timing closure on multiple high-performance, low power designs. Experience in developing and supporting a fully automated STA scripts/flows using Synopsys PrimeTime.  Demonstrate successful results for multiple ASIC programs, is required. Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Synopsys and  Cadence design tools and flows.

Minimum Requirements

• Own the full chip Timing Constraints for a complex, multi-clock, multi-voltage SoC
• Implement the timing flow from frontend (pre-layout) to backend (post-layout) at both chip level and block level
• Develop timing related scripts (tcl/primetime etc.) for clock skew analysis, critical path analysis, various macro interfaces etc.
• Implement timing related scripts for constraints partitioning (from chip level to block level), IO timing budgeting and overall SDC cleanup
• Implement auto ECO (timing) generation scripts/flows to facilitate quicker timing closure

Preferred Requirements

• Familiarity with image processing is a strong plus

Responsibilities

As a senior member of ASIC/SoC design team, you’ll be responsible for full chip timing constraints development, full chip Static Timing Analysis and Signoff for all modes (functional, dft, etc.), streamlining the timing analysis methodologies and flows (primetime, critical path simulation etc.) and develop/enhance auto ECO generation scripts for timing closure.

Support chip level DFT and physical design timing closure.

This Job is located in Silicon Valley / San Jose, CA & Metropolitan Statistical Area. Candidate must have the legal right to work in the USA .

Please refer to Job Number ESE13-0103 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
2150 North First Street, Suite #680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0103
E-mail: hr@esenciatech.com

Job Requirements and Qualification

You must have a BSEE or MSEE with at least 5+ years of applicable experience. Demonstrate successful results for multiple ASIC programs, is required. Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Intel, Synopsys and  Cadence design tools and flows. You need to have solid experience as below:

Minimum Requirements:

• Direct hands-on experience on flip chip CSP and BGA assembly
• Familiar with the quality and reliability test conditions and specifications
• Familiarity with substrate design and design rules
• Ability to work with cross-functional teams to trouble shoot production and field issues.
• Familiarity with various interface technologies including MIPI, USB, I2C, GPIO, DDR etc
• Familiarity with ASIC design flows for deep sub micron technologies

Preferred Requirements:

• Familiarity with image processing is a strong plus

Responsibilities

Candidate will generate/optimize pad ring, bump pattern, pin out, etc for SOC package by working with cross-functional teams including package design, Signal Integrity, Physical Integration and System board design teams. A candidate will design the RDL (Re-distribution layer) and route special signals according to their specification.  Estimate chip / die size.  Work with engineers to identify IO ring and IO voltage domains.  Run spice analysis for throughput measurement.  Familiarity with EM (Electro Migration) and SSO (Simultaneously Switching Output) checks.  Support physical design team and work with foundry/test house.

This Job is located in Silicon Valley / San Jose, CA & Metropolitan Statistical Area. Candidate must have the legal right to work in the USA .

Please refer to Job Number ESE13-0100 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
2150 North First Street, Suite #680
San Jose, CA 95131
ATTN: Human Resources-Job No. ESE13-0100
E-mail: hr@esenciatech.com