Esencia Technologies Announces EScala Design Platform
EScala design platform drastically reduces time to implement high performance computing and signal processing applications
San Jose Calif. – May 14, 2012 – Esencia Technologies, a technology leader in ASIC DSP design, today announced the launch of its breakthrough EScala design platform. The EScala platform drastically reduces the development time required to implement complex, compute-intensive algorithms on a SoC from months to only days.
“EScala’s main objective was to offer relief to OEMs and semiconductor companies that are faced with the challenge of ever-increasing complexity and compute requirements for multimedia algorithms, as well as increased time-to-market pressure,” said Ravi Satrawada, CEO and President of Esencia Technologies. “EScala profoundly shortens the time it takes to implement high-end audio or video algorithms in silicon. Algorithms that take months to architect, design and verify in RTL can be implemented on an EScala design platform in weeks.”
EScala uses C/C++ as a design entry language and automatically generates an application-specific programmable core. With EScala, the designer is able to optimize and scale the generated core to best fit the application’s area, low power and performance profile.
EScala targets algorithms that are currently too demanding to efficiently run on traditional CPUs, like ARM’s Cortex-M or Cortex-R series. A single EScala core offers computational performance that is up to 32 times higher than traditional RISC cores. Additionally the design platform offers built-in support for multi-core architectures that can take on even the most MIPS-hungry algorithms.
Many high-end algorithms have very unique memory bandwidth requirements. EScala supports fully scalable memory interfaces that enable system architects to prevent their cores from being memory bandwidth limited.
Migrating algorithms to EScala is easy. The EScala design platform comes with a full software development environment (SDK) for C and C++ that includes an integrated debugger and simulator. Programmers are not forced to use CPU-specific intrinsics or special libraries to get good performance results. The EScala compiler will take care of optimizations. This is a result of Esencia’s proprietary patent pending optimization technology that is used to generate the cores, as well as its run-time code.
The EScala design platform generates synthesizable RTL code and related scripts to easily integrate it into an ASIC SoCs. It supports standard bus protocols interfaces like AMBA AHB/AXI as well as Wishbone. These interfaces make it easy to integrate EScala cores with the wide variety of available peripheral IPs. To connect tightly coupled high speed RAM, optimized memory interface protocols are available.
EScala was developed and is supported by Esencia Technologies, a company that has a long track record of successful ASIC tape-outs and understands the importance of customer service.
Esencia Technologies will be at DAC 2012, June 4 – 6, 2012 at Moscone Center in San Francisco, Booth #708.
About Esencia Technologies, Inc.
Esencia Technologies, Inc. is a Silicon Valley technology leader in ASIC/FPGA DSP IP and design established in 2006. It has offices in San Jose, California, and Bangalore, India. Esencia Technologies offers ASIC IP and turn-key semiconductor design services, from product specification through GDS2 to production. Our team has completed projects for Fortune 500 companies, as well as small start-ups in leading semi-conductor process nodes. For more information, visit http://esenciatech.com/