ASIC verification methodologies have come a long way over the past few years and are now at a point where we see most of our clients using some form of random constraint testing and assertion. We are using and recommending UVM for verification and base our metrics-driven approach on SystemVerilog support for functional coverage and assertions.
For functional verification coverage, we specify coverage points for each feature indicated in the specification, so there is direct mapping–and hence, there are good metrics–for completeness criteria. However, for assertions, we have not been able to specify such measurable criteria for completeness.
This is partly because assertions aim at states and signal combinations that are not allowed to occur. Most of the specifications I have come across do not consider those in great detail, which then makes it challenging to come up with the right set of assertions quickly.
Therefore, it looks like it pays off to be more rigorous in specifying illegal combination and state transitions in the requirements specification. With this in hand, we are then able to derive the assertions the same way we do for coverage points–and use the same completeness metrics.
I am curious about what other experts practice and have to say about this matter, so please leave a note if you would like to share your thoughts.