Completeness metrics for assertions

ASIC verification methodologies have come a long way over the past few years and are now at a point where we see most of our clients using some form of random constraint testing and assertion. We are using and recommending UVM for verification and base our metrics-driven approach on SystemVerilog support for functional coverage and assertions.

For functional verification coverage, we specify coverage points for each feature indicated in the specification, so there is direct mapping–and hence, there are good metrics–for completeness criteria. However, for assertions, we have not been able to specify such measurable criteria for completeness.

This is partly because assertions aim at states and signal combinations that are not allowed to occur. Most of the specifications I have come across do not consider those in great detail, which then makes it challenging to come up with the right set of assertions quickly.

Therefore, it looks like it pays off to be more rigorous in specifying illegal combination and state transitions in the requirements specification. With this in hand, we are then able to derive the assertions the same way we do for coverage points–and use the same completeness metrics.

I am curious about what other experts practice and have to say about this matter, so please leave a note if you would like to share your thoughts.

Interview – Microelectronics requires expertise and innovation

This is a translation of an interview published in the engineering periodical “Technischen Rundschau.” The original article is in German and can be accessed at: http://www.technische-rundschau.ch/tr/artikel/index.php?id=25702 . A PDF copy is available here.

Technische Rundschau 5/2012,  Micro Manufacturing | Services

Microelectronics requires expertise and innovation?

Karl Kaiser, vice president of engineering of the high-tech company Esencia Technologies, visited the Technical Department of the University of Applied Sciences, Northwestern Switzerland. Michael Pichler, deputy director of the Institute of Microelectronics and head of MAS-Microelectronics, spoke with him about trends and perspectives in microelectronics.

Mr. Kaiser, what products and services does Escencia Technologies offer?

Esencia offers a complete menu of services, from product concept to chip layout. Most of our customers’ products target  wireless, video, encryption, and computing/networking. We specialize in digital signal processing ASICs. Our customers also use our IP blocks to build complex chips in this space.

The University of Applied Sciences, Northwestern Switzerland offers a specific degree in microelectronics. What about Silicon Valley?

Experts from all over the world come to Silicon Valley, all with excellent educations. Some come here to pursue postgraduate degrees. We have many good universities in the Bay Area, like Santa Clara University; San Jose State University; Stanford University; and the University of California, Berkeley. All of them have excellent reputations.

What is the difference between a design engineer and a verification engineer?

A design engineer must know much more about circuits. Verification engineers are typically more interested in object-oriented programming and software design. It is obvious that the progress in verification has been profound over the last few years, and hence, it is much harder to find these kinds of experts.

How do you assess the problem of different design and verification languages?

Each language has its advantages and disadvantages. It seems to me that the biggest problem is that the microelectronics industry cannot converge to a single language. Having to support multiple HDL languages result in higher costs that, at the end of the day, the customer has to pay.

Which ones do you mean?

As design languages, we will see Verilog in the United States and VHDL in Europe and Japan sticking around for a while. I don’t see SystemC or C++ really becoming mainstream design languages.

In the United States, it is already quite clear that SystemVerilog has prevailed as a verification language. After the battle of the three letter acronyms eRM, OVM, AVM, and VMM, the industry seems to have converged on UVM as a verification method based, obviously, on SystemVerilog. Currently, there are efforts to reinvent the same thing again for VHDL.

How does the world of microelectronics look to you in ten years?

In Silicon Valley, ten years is a long time! Given the fast pace of the micro-electronics industry, most high-tech companies only plan about three years ahead. Nevertheless, I dare to suggest a few things.

That is?

Moore’s Law, which postulates the doubling of the number of transistors on a chip every 18 months, will only apply to a few applications, such as chipsets for mobile devices, or CPUs. This is mostly due to the development costs also doubling every 18 months. Hence, fewer and fewer companies are able to afford and justify these expensive technologies and investments.

What about the sectors that do not need the latest process technology?

For those companies that do not require the latest process technology, it has never been cheaper to build their own  semiconductor products. This trend will continue to the point when integrated circuits come out of inkjet printers. Especially for analog circuits, that would be most attractive.

What trends do you see?

In addition to the process technology advances, I see great potential in the area of analog design methodology. Not too much has changed the way analog circuits are designed since the introduction of SPICE . How about designing analog blocks with high-level languages? On the digital side, further steps toward even higher abstraction will allow even more complex chips to be built. Esencia Technologies is very active in this field. We are able to map C/C++ algorithms into reprogrammable IP cores and thus drastically reduce the time it takes to build a system.

It looks like there is still a lot to be expected ….

One thing is certain: In the technological world, development is much different than what might be expected! Innovative engineers and research teams will invent things to draw everything into a new orbit. I am also convinced that engineers will make a lot of important contributions that will help solve some of our social challenges!

University of Applied Sciences, Northwestern Switzerland, 5210 Windisch, Tel +41 56 462 46 76, www.fhnw.ch

Innovation Report 2011

Esencia Technologies is doing business in several geographic regions of the world. We work closely with customers and clients who are engaged in innovative product development projects. Innovation is not only key for our customers; it is also Esencia’s number one priority. Therefore, it is quite interesting for us to review the recently published Global Innovation Index (GII).

The Global Innovation Index (GII) is a research project conducted by INSEAD. The research measures innovativeness in 125 economies. This year’s report, available at www.globalinnovationindex.org, ranked Switzerland as the world’s most innovative nation, followed by Sweden, Singapore, Hong Kong (SAR), Finland, and Denmark — and the U.S., in seventh place.

It is difficult to precisely measure innovation, not only on a global macro level, but in the details of day-to-day engineering work. Only time will tell which countries and companies can pull ahead, capitalizing on innovation.

Esencia’s IP solutions like EScala are packed with innovation, and our engineers strive for innovative solutions on every task they pick up. Even though innovation may be difficult to measure, it is still easy to identify when you see it.