Posts Comments

Completeness metrics for assertions

ASIC verification methodologies have come a long way over the past few years and are now at a point where we see most of our clients using … [Read More...]

State of RTL based design – is it time to move beyond?

Abstract Synopsys is celebrating its 25th anniversary this year. This also means that availability of commercial logic synthesis is turning … [Read More...]

EScala Design Platform
Accellerate your algorithm development!
EScala uses C/C++ as a design entry language and automatically generates an application-specific reprogrammable core.

With EScala the designer is able to optimize and scale the generated core to best fit the application’s area, low power and performance profile.

DSP IP Cores
  • FFT 1024/512: Low latency, dynamically configurable as 1024 or 512 points FFT and IFFT.
  • Viterbi Decoder: Viterbi Algorithm for 802.11 a/b/g standard
  • AES: High speed Advanced Encryption Standard.
  • Fixed point DSP RTL & Matlab library
  • Pre-processors for Matlab and Verilog code

Design Services
  • Wireless, Networking, and Video architecture
  • IP Core development, customization and integration
  • Turn-key project development
  • On-site consulting for design and verification