Esencia simplifies your RTL development
 
Implementing complex algorithms in silicon needs massive RTL development and gigantic verification effort. And meeting the RTL freeze deadlines had always been a major challenge considering the design complexities and the resource requirements.
 
Esencia’s purpose is to simplify this RTL development with pre-verified soft IP’s, smart technologies and experienced design services. Esencia technologies is a leading provider of IP cores and Technologies to dramatically reduce time-to-market.

 
 
• C++ to Synthesizable RTL
• Fixed point DSP RTL & Matlab library
• Pre-processors for Matlab and Verilog code
 
 
 
• FFT 1024/512:  Low latency, dynamically configurable as 1024 or 512 points FFT and IFFT.
• Viterbi Decoder: Viterbi Algorithm for 802.11 a/b/g standard
• AES: High speed Advanced Encryption Standard.
 
 
• Wireless, Networking, and Video architecture
• IP Core development, customization and integration
• Turn-key project development
• On-site consulting for design and verification

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